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FUNCTIONAL INTERNAL BLOCK DESCRIPTION
INTRODUCTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
LOGIC INPUTS
AND INTERFACE
LOW-SIDE
DRIVERS
BOOTSTRAP
SUPPLY
HIGH-SIDE
DRIVERS
CHARGE
PUMP
Figure 10. Functional Internal Block Description
All functions of the IC can be described as the following
five major functional blocks:
? Logic Inputs and Interface
? Bootstrap Supply
? Low-Side Drivers
? High-Side Drivers
? Charge Pump
LOGIC INPUTS AND INTERFACE
This section contains the SPI port, control logic, and shoot-
through timers.
The IC logic inputs have Schmitt trigger inputs with
hysteresis. Logic inputs are 3V compatible. The logic outputs
are driven from the internal supply of approximately 5.0V.
When the internal supply is not enabled, the SO pin should
not be externally driven high.
The SPI registers and functionality is described completely
in the LOGIC COMMANDS AND REGISTERS section of this
document. SPI functionality includes the following:
? Programming of deadtime delay —This delay is
adjustable in approximately 50 ns steps from 0 ns to
12 μs. Calibration of the delay, because of internal IC
variations, is performed via the SPI.
? Enabling of simultaneous operation of high-side and
low-side FETs —Normally, both FETs would not be
enabled simultaneously. However, for certain applications
where the load is connected between the high-side and
low-side FETs, this could be advantageous. If this mode is
enabled, the blanking time delay will be disabled. A
sequence of commands may be required to enable this
function to prevent inadvertent enabling. In addition, this
command can only be executed once after reset to enable
or disable simultaneous turn-on.
? Setting of various operating modes of the IC and
enabling of interrupt sources.
The 33927 allows different operating modes to be set and
locked by a SPI command (FULLON, Desaturation Fault,
Zero-Deadtime). SPI commands can also determine how
the various faults are (or are not) reported.
? Read back of internal registers .
The status of the 33927 Status Registers can be read back
by the Master (DSP or MCU).
The Px_HS and Px_LS logic inputs are edge sensitive.
This means the leading edge on an input will cause the
complementary output to immediately turn off and the
selected one to turn on after the deadtime delay as illustrated
in Figure 11 . The deadtime delay timer starts when the
corresponding FET was commanded off (see Figure 6 and
Figure 11 ).
PA _HS
PA_LS
De adt ime
De lay
PA_HS_G
PA_LS_G
Figure 11. Edge Sensitive Logic Inputs (Phase A)
BOOTSTRAP SUPPLY (VPWR)
This is the portion of the IC providing current to recharge
the bootstrap capacitors. It also supplies the peak currents
required for the low-side gate drivers.
The power for the gate drive circuits is provided through
the VPWR pin. This pin can be connected to VBAT and is
capable of withstanding up to the full load dump voltage of the
system. However, the IC only requires a low-voltage supply
33927
Analog Integrated Circuit Device Data
24
Freescale Semiconductor
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